To maintain data integrity memory in dynamic random access memory (DRAM), DRAM cells are refreshed periodically. A retention time of DRAM cells is a function of operating temperature and random manufacturing variations. As temperature increases, the DRAM cells discharge more rapidly thereby reducing the amount of time data are retained in those cells. As a result, to reliably maintain data, thermally hotter DRAM cells need to be refreshed more often than colder DRAM cells. While the required refresh time of a DRAM cell is partly a function of temperature, manufacturing variations exist between each DRAM cell and thereby each subarray, bank, and vault in a DRAM die also contribute to the refresh time needed for a particular DRAM cell. DRAM cell variation can be both purely random (e.g., every DRAM cell is somewhat different) and parametric (e.g., DRAM cells near to one another perform similarly). Accordingly, even at similar temperatures, different storage locations in a DRAM need to be refreshed at different rates. However, according to conventional schemes, entire regions of DRAM are refreshed at a same rate.
DRAM cells of a row cannot be accessed while the row is being refreshed, so time spent refreshing DRAM cells can reduce overall performance of memory-accessing workloads. High DRAM cell density combined with DRAM cell retention-time variability results in DRAM refresh becoming a severe performance bottleneck under certain conditions. Complicating the situation, die or other layers of DRAM cells often are stacked together directly on top of each other to form a stacked DRAM, which in turn often is stacked on top of heat-generating logical components such as central processing units (CPUs) and graphics processing units (GPUs), thereby increasing refresh rates when decreased refresh rates are desired.
Conventional data placement within available DRAM cells is agnostic to variations in DRAM retention times thereby resulting in a sub-optimal data placement when considering certain operational characteristics of stacked DRAM and the character of the data therein. Different sections and different layers of stacked DRAM are exposed to different temperatures depending on a variety of factors including the particular geometry of the components and their respective heat-producing workloads, locations of heatsinks, amount of contact with other components, and the physical design of the DRAM layers and components therein.